1. Field of the Invention
The present invention generally relates to data-transfer systems using a bus, and particularly relates to a data-transfer system which drives a bus with signals of a small amplitude.
2. Description of the Related Art
As a processing speed of microprocessors is enhanced, a data transfer between LSI chips is expected to have an increased data-transfer speed based on an increased signal frequency. However, use of the TTL level or the CMOS level, which are input/output levels of the prior-art LSI, suffers an increased influence of signal reflection and crosstalk as a signal frequency begins to exceed about 50 MHz. In such a case, it is difficult to conduct errorless data transfer.
In order to overcome this problem, various input/output interfaces have been proposed, including GTL (Gunning transceiver logic), SSTL (sub series terminated logic), RAMBUS, etc.
These input/output interfaces suppress signal reflection at the ends of a bus by terminating the bus with termination resistances (anti-signal-reflection resistances), and use small-amplitude signals having an amplitude smaller than 1 V. This is because use of small-amplitude signals generally enables high-speed data transfer since a signal frequency which can be transferred is reciprocal to the amplitude voltage.
In the prior-art input/output interfaces such as GTL, SSTL, RAMBUS, and the like, however, a voltage level of the bus is not stable because of the connection of the bus to the terminal voltage V.sub.TT via the terminal resistances.
FIG. 1 is an illustrative drawing showing a system configuration of the SSTL. In the SSTL, as shown in FIG. 1, an output circuit 200 is coupled to a bus 201 via a stub resistance Rs, and the bus 201 is connected to a termination voltage V.sub.TT via termination resistances R.sub.TT. The termination resistances R.sub.TT are provided in order to suppress signal reflection at the ends of the bus 201, and the stub resistance Rs is used for reducing signal reflection between a stub (a branch stemming from the bus 201) 202 and the bus 201. A bus configuration of the GTL is the same as that of FIG. 1, except for the existence of the stub resistance Rs.
Assume that a PMOS transistor 205 and an NMOS transistor 206 in the output circuit 200 are turned off and on, respectively, in the SSTL system of FIG. 1. In this case, the output circuit 200 outputs a low-level signal. A voltage V.sub.SS of the output circuit 200 is coupled to the termination voltage V.sub.TT via an on-resistance (turn-on resistance) of the NMOS transistor 206, the stub resistance Rs, and the termination resistances R.sub.TT. Namely, the voltage of the bus 201 is determined as a voltage at a middle point of a resistance series. Because of this, variations of the on-resistance of the transistor, the stub resistance Rs, and the termination resistances R.sub.TT contribute to a variation in the voltage of the bus 201.
A variation of the bus voltage due to variations of the transistor on-resistance, the termination resistances R.sub.TT, and the like is similarly observed in other input/output interfaces such as the GTL, RAMBUS, or the like.
With a variation of a bus voltage, an operation voltage of the system cannot be set to a minimum voltage with which the system can operate, and, thus, the system should be allowed to operate with a large amplitude to provide a margin to some extent. In this case, use of small-amplitude signals by terminating the bus with termination resistances will be compromised, and the signal transfer based on a desired small amplitude becomes difficult. In order to avoid this, RAMBUS, for example, is provided with a compensation circuitry for suppressing the bus-voltage variation. This compensation circuitry, however, adds to the complexity of the entire circuit, and requires a manufacturing process of high technology.
Another problem commonly associated with the input/output interfaces such as GTL, SSTL, RAMBUS, and the like is that the bus connection to the termination voltage via the termination resistances entails generation of a DC current when the signal level of the bus is either a high level or a low level. This DC current brings about excessive power consumption, which is as much as about 15 mW per output pin. In a situation where an emphasis is placed on a reduction in power consumption as in the application to portable equipment, such excessive power consumption is not desirable.
Accordingly, there is a need for a high-speed data transfer system which can use small-amplitude signals without requiring termination via termination resistances.